The present invention relates to a graphic processor for producing pattern display data for use in, for example, a CRT display device.
In a pattern display system for displaying a pattern by a group of dots, a straight line is displayed by a line of dots such as shown in FIG. 1. FIG. 1 shows the case where a display plane is divided into 1024 equal parts in each of transverse and longitudinal directions, namely, in the direction of each of X- and Y-axes. In FIG. 1, coordinates are assigned to the display plane in such a manner that divisions placed in the upper left, upper right, lower left and lower right corners have coordinates (0, 0), (1023, 0), (0, 1023) and (1023, 1023), respectively. The so-called refresh memory has memory areas which correspond to divisions on the display plane in a one-to-one relation and store display data. The refresh memory is accessed in synchronism with the scanning operation in a CRT display device.
A graphic processor shown in FIG. 2 has hitherto been used to display patterns. Referring to FIG. 2, a vector generator 1 converts a line segment to be displayed into a line of dots, and sets the X- and Y-coordinates of each dot in an X-address register 2 and a Y-address register 3, respectively. The vector generator 1 delivers not only the above-mentioned X- and Y-coordinates but also pattern data indicating the color of the line segment. The pattern data from the vector generator 1 is not supplied to a refresh memory 5 but is written in a refresh memory buffer (hereinafter simply referred to as "buffer") 4 at a position specified by the lower n bits of each of the X-address register 2 and Y-address register 3. The buffer 4 has a pattern data storing area corresponding to that partial region on the display face of the CRT which is formed of 2.sup.n .times.2.sup.n dots (for example, n=3). When the vector generator 1 generates pattern data in a different partial region in addition to pattern data in a desired partial region, an overflow detecting circuit 6 detects such a situation, and the pattern data stored in the buffer 4 (and corresponding to 2.sup.n .times.2.sup.n dots) is written in the refresh memory 5 in parallel. Thereafter, the same operation is performed for each of the other partial regions, and pattern data is successively written in the refresh memory 5. Thus, all of the pattern data to be displayed on the display face are written in the refresh memory 5. The buffer 4 is provided to eliminate the waiting time of the vector generator 1 caused by the low writing speed for the refresh memory 5. In more detail, since the operating speed of the vector generator 1 is higher than that of the refresh memory 5, the output of the vector generator 1 is temporarily stored in the buffer 4, and then the contents of the buffer 4 are written in the refresh memory 5 in parallel, thereby preventing the vector generator 1 from being stopped.
According to such a prior art device, however, when a pattern is displayed in a plurality of colors, a plurality of bits are necessary for indicating the kind of color, and a number of buffers equal to the number of colors are required.
Further, in the prior art, pattern data corresponding to 2.sup.n .times.2.sup.n dots are written in a partial area of the refresh memory 5 in parallel, and therefore pattern data having already been written in the partial area are erased by new pattern data being written.
Furthermore, when pattern data overflows the buffer 4 and the contents of the buffer 4 are transferred to the refresh memory 5 in parallel, the buffer 4 must hold the pattern data till all of the pattern data in the buffer 4 has been written in the refresh memory 5. The writing operation of the vector generator 1 for the buffer 4 is stopped for this period, and therefore an undesirable waiting time is required.
In addition, in the case where pattern data is written in only an edge portion of the buffer 5, an overflow is caused by writing the pattern data of only a few dots in the buffer, and thus a writing operation for the refresh memory 5 is required. Accordingly, the vector generator 1 must wait till the writing operation for the refresh memory 5 is completed, and is kept at the stand-by state for a longer time than the operating time thereof.